The building block for the conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology consists of N-channel Metal-Oxide-Semiconductor Field-Effect Transistors (NMOSFETs) and P-channel Metal-Oxide-Semiconductor Field-Effect Transistors (PMOSFETs). The NMOSFETs and PMOSFETs are normally in a nonconductive state (e.g., an off state) when a gate voltage of the transistors does not exceed a gate threshold value. To operate a MOSFET in a conductive state (e.g., an on state), a sufficiently large gate threshold voltage (Vth) typically needs to be applied to a gate electrode of the MOSFET (e.g., relative to a voltage of the source electrode of the MOSFET). Normally, Vth is positive for NMOSFETs, and negative for PMOSFETs.
Typically, the drive current of either the NMOSFET or the PMOSFET is approximately proportional to its carrier mobility (μ) and channel width (W). Since the mobility of electrons (μe) is different from the mobility of holes (μp) for a given semiconductor material, the width of the PMOSFET (Wp) is often different than that the width (Wn) of the NMOSFET in CMOS circuits so that each transistor is designed to produce the same amount of current in the CMOS circuit. More specifically, the Wp/Wn ratio is typically set to be the mobility ratio of μe/μp for the purpose of current matching in CMOS circuits. For example, to achieve current matching in silicon-based CMOS logic circuits, the width of the PMOSFET is typically 2-3 times that of the NMOSFET, corresponding to the μe/μp ratio of silicon, for current matching. However, even with adjusted widths, the speed of a CMOS circuit is ultimately limited by the transistors in the circuit with lower carrier mobility, as the large width will also increase the load capacitances in cascaded logic gates, and hence reduce the overall speed.
For semiconductor materials that have a large gap between μe and μp values, the speed of the CMOS circuit is limited by the μ having the lowest value, and the drain current to pull-up and pull-down does not match unless an unrealistically large width ratio is applied. Unfortunately, the imbalance between μe and μp is common in those emerging semiconductor substrates to replace Si, as shown in Table I below. Moreover, some special semiconductor substrates, such as InGaZnO, CdSe, carbon nanotube (CNT), and 2D transition metal dichalcogenides (TMDs), do not have complementary-type doping for CMOS circuits (i.e., do not support NMOSFET AND PMOSFET devices). Thus, for these channel materials, unipolar logic is the only realistic option since unipolar logic circuits incorporate either N-type devices or P-type devices, but not both.
TABLE Ishows the electron and hole mobility for a number of semiconductors, indicating large μe/μp ratios for many of them.SiGeGaAsIn0.53Ga0.47AsInAsEg (eV)1.10.661.40.750.35μn (cm2/v-s)1,3503,9004,6007,80040,000μp (cm2/v-s)480l,900500350<500m*/mo0.1650.120.0670.0410.024
Conventional unipolar logic circuits often include depletion load NMOS (or PMOS) logic and/or pass-gate logic with various swing restoration techniques. Depletion load NMOS logic can have high static power consumption, which can be undesirable for many application. Pass-gate logic circuits are often only pseudo-unipolar as they tend to rely on CMOS circuits including both NMOSFET and PMOSFET devices to achieve full swing, which adds cost and complexity to the design of logic circuits.
All-N-channel CMOS logic circuits (i.e. unipolar logic circuits) have been developed some of which are described in U.S. Pat. No. 8,384,156, the disclosure of which is incorporated by reference herein in its entirety. Similar unipolar logic circuits can be recognized using only on PMOSFETs device. In unipolar logic circuits, transistors of the same type (i.e., either NMOSFETs or PMOSFETs) are used to both pull up and pull down output voltage levels, but the gates of the pull-up and pull-down transistors are driven complementary inputs.
It has been recognized that a “weak-high” problem exists in unipolar logic circuits when a NMOSFET (or PMOSFET) is used to pull up (or down) the voltage level. The weak high problem can also be characterized as Vth-loss problem because the resulting output voltage is typically at best Vdd-Vth for NMOSFET unipolar logic circuits (or Ground+Vth for PMOSFET unipolar logic circuits), which is a |Vth| below a desired voltage level for a NMOSFET unipolar logic circuit or a |Vth| above a desired voltage level for PMOSFET unipolar logic circuits. Conventional pass gate logic circuits often adapt conventional CMOS circuits at an output stage of the logic to recover the output levels to overcome the weak high problem. In doing so, such conventional pass gate logic circuits include both N-type and P-type devices and, therefore, are no longer unipolar circuits.